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一种针对Cache Tag单错及邻位双错的低开销容错方法

A Low-Cost Single Error and Double-Adjacent Error Correction Fault Tolerance method for Cache Tag
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摘要 Cache是处理器重要的存储模块,对处理器性能提升有着至关重要的作用.空间环境中,保护Cache免受软错误影响已成为设计新一代高可靠微处理器日益严峻的挑战.设计一种针对Cache Tag单错及邻位双错的低开销容错方法.可以保证Cache访问、Cache行填充和Cache行回写不受单位错误和邻位双错的影响,与传统SEC-FastTag容错方法相比,Tag单位及邻位双错容错能力得到提高.通过扩展FastTag结构优化设计,降低SEC-DAEC编解码逻辑带来的面积、功耗以及性能方面的开销.以四路组相连写回Cache为目标系统,与传统SEC-DAEC容错方法相比,本文提出的方法面积开销降低8.47%,功耗开销降低37.7%,关键路径时延减小0.13 ns. As an important memory in processor,Cache plays a vital role in processor performance improvement.Protecting Cache from soft errors in harsh space environment has become an increasingly serious challenge for highly reliable micro-processor designing.A low-cost single and double-adjacent error correction fault tolerance method is proposed for Cache Tag,which can guarantee the Cache access,linefill and write-back are not affected by single bit error and double adjacent error.And compared with traditional SEC-Fast Tag,the capability of fault tolerance on single bit error and double-adjacent error is improved.Through extend-Fast Tag designing,the proposed method can reduce the area,power and performance overhead brought by SEC-DAEC.Testing on a 4-ways set-associative Cache,compared with the traditional SEC-DAEC fault-tolerant method,the proposed method reduces the area overhead by 8.47%,the power consumption overhead by 37.7%,and the critical path delay by 0.13 ns.
作者 梁贤赓 华更新 高瑛珂 LIANG Xiangeng;Hua Gengxin;Gao Yingke(Beijing Institute of Control Engineering,Beijing 100090,China)
出处 《空间控制技术与应用》 CSCD 北大核心 2020年第1期60-65,共6页 Aerospace Control and Application
基金 北京市科学技术委员会资助项目(Z191100004619003)。
关键词 CACHE TAG 容错 SEC-FastTag SEC-DAEC 扩展FastTag cache Tag fault tolerance SEC-FastTag SEC-DAEC extend-fastTag
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  • 1王新梅,肖国镇编著..纠错码:原理与方法 修订版[M].西安:西安电子科技大学出版社,2001:534.
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