期刊文献+
共找到18篇文章
< 1 >
每页显示 20 50 100
Radiation Resistance of Fluorine-Implanted PNP Using Gated-Controlled Lateral PNP Transistor Structure
1
作者 王信 陆妩 +6 位作者 马武英 郭旗 王志宽 何承发 刘默寒 李小龙 贾金成 《中国物理快报:英文版》 SCIE CAS CSCD 2016年第8期85-87,共3页
The radiation damage responses of Buorinated and non-Buorinated lateral PNP transistors are studied with specially designed gated-controUed lateral PNP transistors that allow for the extraction of the oxide trapped ch... The radiation damage responses of Buorinated and non-Buorinated lateral PNP transistors are studied with specially designed gated-controUed lateral PNP transistors that allow for the extraction of the oxide trapped charge(Not)and interface trap(Nt)densities.All the samples are exposed in the Co-60γray with the dose rate of 0.5 Gy(Si)/s.After the irradiation,the buildup of N_(ot)and N_(it)of the samples with total dose is investigated by the gate sweep test technique.The results show that the radiation resistance of Buorinated lateral PNP transistors is signiBcantly enhanced compared with the non-Buorinated ones. 展开更多
关键词 PNP晶体管 氟化 控制 管结构 抗辐射 门控 植入 界面陷阱密度
Solution-Processed High Mobility Top-Gate N-Channel Polymer Field-Effect Transistors
2
作者 项兰义 应俊 +2 位作者 韩金花 王伟 谢文法 《中国物理快报:英文版》 SCIE CAS CSCD 2015年第9期167-170,共4页
关键词 场效应晶体管 聚合物晶体管 N沟道 加工流动性 顶栅 聚(甲基丙烯酸甲酯) 界面陷阱密度 操作电压
Effects of interface trap density on the electrical performance of amorphous InSnZnO thin-film transistor
3
作者 梁永烨 Kyungsoo Jang +2 位作者 S.Velumani Cam Phu Thi Nguyen Junsin Yi 《半导体学报:英文版》 EI CAS CSCD 2015年第2期82-86,共5页
We reported the influence of interface trap density(Nt) on the electrical properties of amorphous InSnZnO based thin-film transistors,which were fabricated at different direct-current(DC) magnetron sputtering powe... We reported the influence of interface trap density(Nt) on the electrical properties of amorphous InSnZnO based thin-film transistors,which were fabricated at different direct-current(DC) magnetron sputtering powers.The device with the smallest Nt of 5.68×1011 cm-2 and low resistivity of 1.21×10-3Ω·cm exhibited a turn-on voltage(VON) of-3.60 V,a sub-threshold swing(S.S) of 0.16 V/dec and an on-off ratio(ION/IOFF) of8 x 108.With increasing Nt,the VON,S.S and ION/IOFF were suppressed to-9.40 V,0.24 V/dec and 2.59×108,respectively.The VTH shift under negative gate bias stress has also been estimated to investigate the electrical stability of the devices.The result showed that the reduction in Nt contributes to an improvement in the electrical properties and stability. 展开更多
关键词 界面陷阱密度 薄膜晶体管 电性能 非晶 溅射功率 低电阻率 偏压应力 OFF
Effects of wet-ROA on shallow interface traps of n-type 4H-SiC MOS capacitors
4
作者 朱巧智 王德君 《半导体学报:英文版》 EI CAS CSCD 2014年第2期32-35,共4页
The effects of wet re-oxidation annealing(wet-ROA) on the shallow interface traps of n-type 4H-SiC metal–oxide–semiconductor(MOS) capacitors were investigated by Gray–Brown method and angle-dependent Xray photoelec... The effects of wet re-oxidation annealing(wet-ROA) on the shallow interface traps of n-type 4H-SiC metal–oxide–semiconductor(MOS) capacitors were investigated by Gray–Brown method and angle-dependent Xray photoelectron spectroscopy technique. The results present the energy distribution of the density of interface traps(Dit/ from 0 to 0.2 eV below SiC conduction band edge(EC/ of the sample with wet-ROA for the first time,and indicate that wet-ROA could reduce the Dit in this energy range by more than 60%. The reduction in Dit is attributed to the reaction between the introduced oxygen and the SiOxCy species,which results in C release and SiOxCy transformation into higher oxidation states,thus reducing the SiOxCy content and the SiOxCy interface transition region thickness. 展开更多
关键词 界面陷阱密度 4H-SIC MOS电容 X射线光电子能谱法 金属氧化物半导体 n-型 界面过渡区 能量分布
Impact of nitrogen plasma passivation on the interface of germanium MOS capacitor
5
作者 云全新 黎明 +9 位作者 安霞 林猛 刘朋强 李志强 张冰馨 夏宇轩 张浩 张兴 黄如 王阳元 《中国物理B:英文版》 SCIE EI CAS CSCD 2014年第11期616-619,共4页
Nitrogen plasma passivation(NPP) on(111) germanium(Ge) was studied in terms of the interface trap density,roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition(PECVD). The results ... Nitrogen plasma passivation(NPP) on(111) germanium(Ge) was studied in terms of the interface trap density,roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition(PECVD). The results show that NPP not only reduces the interface states, but also improves the surface roughness of Ge, which is beneficial for suppressing the channel scattering at both low and high field regions of Ge MOSFETs. However, the interfacial layer thickness is also increased by the NPP treatment, which will impact the equivalent oxide thickness(EOT) scaling and thus degrade the device performance gain from the improvement of the surface morphology and the interface passivation. To obtain better device performance of Ge MOSFETs, suppressing the interfacial layer regrowth as well as a trade-off with reducing the interface states and roughness should be considered carefully when using the NPP process. 展开更多
关键词 界面陷阱密度 氮等离子体 MOS电容 钝化 MOSFET 界面层厚度 表面粗糙度 等效氧化层厚度
Effect of re-oxidation annealing process on the SiO2/SiC interface characteristics
6
作者 闫宏丽 贾仁需 +2 位作者 汤晓燕 宋庆文 张玉明 《半导体学报:英文版》 EI CAS CSCD 2014年第6期128-131,共4页
The effect of the different re-oxidation annealing(ROA) processes on the SiO2/SiC interface characteristics has been investigated. With different annealing processes, the flat band voltage, effective dielectric charge... The effect of the different re-oxidation annealing(ROA) processes on the SiO2/SiC interface characteristics has been investigated. With different annealing processes, the flat band voltage, effective dielectric charge density and interface trap density are obtained from the capacitance–voltage curves. It is found that the lowest interface trap density is obtained by the wet-oxidation annealing process at 1050 C for 30 min, while a large number of effective dielectric charges are generated. The components at the SiO2/SiC interface are analyzed by X-ray photoelectron spectroscopy(XPS) testing. It is found that the effective dielectric charges are generated due to the existence of the C and H atoms in the wet-oxidation annealing process. 展开更多
关键词 退火工艺 接口特性 再氧化 工艺效果 有效介电常数 X-射线光电子能谱 界面陷阱密度 电荷密度
Interfacial characteristics of Al/Al2O3/ZnO/n-GaAs MOS capacitor
7
作者 刘琛 张玉明 +1 位作者 张义门 吕红亮 《中国物理B:英文版》 SCIE EI CAS CSCD 2013年第7期406-409,共4页
The interfacial characteristics of Al/Al2O3/ZnO/n-GaAs metal-oxide-semiconductor (MOS) capacitor are investigated. The results measured by X-ray photoelectron spectroscopy (XPS) and high-resolution transmission electr... The interfacial characteristics of Al/Al2O3/ZnO/n-GaAs metal-oxide-semiconductor (MOS) capacitor are investigated. The results measured by X-ray photoelectron spectroscopy (XPS) and high-resolution transmission electron microscopy (HRTEM) show that the presence of ZnO can effectively suppress the formations of oxides at the interface between the GaAs and gate dielectric and gain smooth interface. The ZnO-passivated GaAs MOS capacitor exhibits a very small hysteresis and frequency dispersion. Using the Terman method, the interface trap density is extracted from C-V curves. It is found that the ZnO layer can effectively improve the interface quality. 展开更多
关键词 MOS电容 界面特性 高分辨透射电子显微镜 X-射线光电子能谱 界面陷阱密度 GaAs HRTEM 界面质量
The total ionizing dose effects of non-planar triple-gate transistors
8
作者 刘诗尧 贺威 +1 位作者 曹建民 黄思文 《半导体学报:英文版》 EI CAS CSCD 2013年第9期49-52,共4页
This paper investigates the total ionizing dose response of different non-planar triple-gate transistor structures with different fin widths. By exposing the pseudo-MOS transistor to different amounts of radiation, di... This paper investigates the total ionizing dose response of different non-planar triple-gate transistor structures with different fin widths. By exposing the pseudo-MOS transistor to different amounts of radiation, different interface trap densities and trapped-oxide charges can be obtained. Using these parameters together with Altal 3D simulation software, the total dose radiation response of various non-planar triple-gate devices can be simulated. The behaviors of three kinds of non-planar devices are compared. 展开更多
关键词 MOS晶体管 总剂量效应 非平面 栅极 界面陷阱密度 模拟软件 平面器件 剂量响应
Characterization of Al2O3/GaN/AIGaN/GaN metal- insulator-semiconductor high electron mobility transistors with different gate recess depths*
9
作者 Ma Xiao-Hua Pan Cai-Yuan +6 位作者 Yang Li-Yuan Yu Hui-You Yang Ling Quan Si Wang Hao Zhang Jin-Cheng Hao Yue 《中国物理B:英文版》 SCIE EI CAS CSCD 2011年第2期458-464,共7页
关键词 高电子迁移率晶体管 半导体 绝缘体 金属 HEMT器件 界面陷阱密度 槽深 表征
Frequency dispersion effect and parameters extraction method for novel HfO2 as gate dielectric
10
作者 LIU HongXia KUANG QianWei +2 位作者 LUAN SuZhen ZHAO Aaron TALLAVARJULA Sai 《中国科学:信息科学(英文版)》 SCIE EI 2010年第4期878-884,共7页
有 ALCVD (原子层化学药品蒸汽免职) 种的 HfO2/SiO2/p-Si 的瞬间电容器的电的特征被调查。C-V 弄弯累积电容在高频率在频率分散上进行的表演。为有极端薄 HfO2/SiO2 门栈的瞬间电容器,不同制造过程和测量设备将引起寄生效果。这里,... 有 ALCVD (原子层化学药品蒸汽免职) 种的 HfO2/SiO2/p-Si 的瞬间电容器的电的特征被调查。C-V 弄弯累积电容在高频率在频率分散上进行的表演。为有极端薄 HfO2/SiO2 门栈的瞬间电容器,不同制造过程和测量设备将引起寄生效果。这里,能消除频率分散效果的一个相等的电路模型被建议。因为体积缺点和接口状态,在高频率的 C-V 特征曲线显示出一些失真。这份报纸讨论高频率瞬间 C-V 典型曲线的失真。处理方法的一个数据在乐队差距被预付并且连接陷井密度分发被介绍。由把理想的 C-V 曲线与试验性的 C-V 曲线作比较,瞬间电容器的典型电的参数被提取,包括在 SiO2/Si 接口的扁平乐队的电压,氧化物费用和接口陷井的密度的移动。 展开更多
关键词 频散效应 二氧化铪 提取方法 MOS电容器 HFO2/SIO2 界面陷阱密度 SIO2/SI 介电
An analytical model for the cut off frequency and noise of AIGaN/GaN high electron mobility transistor (HEMTs) 预览
11
作者 Rajab Yahyazadeh Zahra Hashempour +1 位作者 Manouchehr Kalafi Mohammad Reza Aboulhasani 《材料科学与工程:中英文版》 2009年第12期 22-25,共4页
关键词 HEMT器件 高电子迁移率晶体管 计算模型 截止频率 噪声分析 GaN 界面陷阱密度 氮化镓
在线阅读 下载PDF
Boundary condition and initial value effects in the reaction-diffusion model of interface trap generation/recovery
12
作者 罗勇 黄大鸣 +1 位作者 刘文军 李名复 《半导体学报:英文版》 EI CAS CSCD 北大核心 2009年第7期70-75,共6页
A simple standard reaction-diffusion(RD) model assumes an infinite oxide thickness and a zero initial interface trap density, which is not the case in real MOS devices.In this paper, we numerically solve the RD model ... A simple standard reaction-diffusion(RD) model assumes an infinite oxide thickness and a zero initial interface trap density, which is not the case in real MOS devices.In this paper, we numerically solve the RD model by taking into account the finite oxide thickness and an initial trap density.The results show that trap generation/ passivation as a function of stress/recovery time is strongly affected by the condition of the gate-oxide/poly-Si boundary.When an absorbent boundary is considered, the RD model is more consistent with the measured interfacetrap data from CMOS devices under bias temperature stress.The results also show that non-negligible initial traps should affect the power index n when a power law of the trap generation with the stress time, tn, is observed in the diffusion limited region of the RD model. 展开更多
关键词 界面陷阱密度 反应扩散 边界条件 模型 初始值 氧化层厚度 恢复时间 有限区域
Capacitance-voltage characterization of fully silicided gated MOS capacitor
13
作者 王保民 茹国平 +3 位作者 蒋玉龙 屈新萍 李炳宗 刘冉 《半导体学报:英文版》 EI CAS CSCD 北大核心 2009年第3期46-51,共6页
This paper investigates the capacitance-voltage(C-V) measurement on fully silicided(FUSI) gated metal-oxide-semiconductor(MOS) capacitors and the applicability of MOS capacitor models.When the oxide leak-age current o... This paper investigates the capacitance-voltage(C-V) measurement on fully silicided(FUSI) gated metal-oxide-semiconductor(MOS) capacitors and the applicability of MOS capacitor models.When the oxide leak-age current of an MOS capacitor is large,two-element parallel or series model cannot be used to obtain its real C-V characteristic.A three-element model simultaneously consisting of parallel conductance and series resistance or a four-element model with further consideration of a series inductance should be used.We employed the three-element and the four-element models with the help of two-frequency technique to measure the Ni FUSI gated MOS capacitors.The results indicate that the capacitance of the MOS capacitors extracted by the three-element model still shows some frequency dispersion,while that extracted by the four-element model is close to the real capacitance,showing little frequency dispersion.The obtained capacitance can be used to calculate the dielectric thickness with quantum effect correction by NCSU C-V program.We also investigated the influence of MOS capacitor's area on the measurement accuracy.The results indicate that the decrease of capacitor area can reduce the dissipation fac-tor and improve the measurement accuracy.As a result,the frequency dispersion of the measured capacitance is significantly reduced,and real C-V characteristic can be obtained directly by the series model.In addition,this pa-per investigates the quasi-static C-V measurement and the photonic high-frequency C-V measurement on Ni FUSI metal gated MOS capacitor with a thin leaky oxide.The results indicate that the large tunneling current through the gate oxide significantly perturbs the accurate measurement of the displacement current,which is essential for the quasi-static C-V measurement.On the other hand,the photonic high-frequency C-V measurement can bypass the leakage problem,and get reliable low-frequency C-V characteristic,which can be used to evaluate whether the full silicidation has completed or not,and to extract 展开更多
关键词 MOS电容 电压特性 金属氧化物半导体 界面陷阱密度 测量精度 SIO2/SI 化控 全硅
用比例差分方法从NMOSFET输出特性提取界面陷阱密度 预览
14
作者 张贺秋 许铭真 谭长华 《北京大学学报:自然科学版》 CAS CSCD 北大核心 2004年第3期417-423,共7页
在均匀的高电场应力下,MOSFET器件的阈值电压和输出特性的比例差分峰值会有所改变。这是由于在应力过程中产生的缺陷引起的。在本文中,用比例差分方法从NMOSFET器件的输出特性提取了阈值电压、输出特性的比例差分的峰值和界面陷阱密... 在均匀的高电场应力下,MOSFET器件的阈值电压和输出特性的比例差分峰值会有所改变。这是由于在应力过程中产生的缺陷引起的。在本文中,用比例差分方法从NMOSFET器件的输出特性提取了阈值电压、输出特性的比例差分的峰值和界面陷阱密度。得到了阈值电压和比例差分峰值,界面陷阱密度和应力时间的关系。此种方法也适用于PMOSFET器件。这是一个简单而快捷的技术。用这个技术实验数据可以在测量的过程中进行分析。 展开更多
关键词 界面陷阱密度 高电场应力 比例差分 MOSFET
在线阅读 免费下载
准静态C—V测量中的工频噪声滤除新方法 预览
15
作者 李同合 陈光遂 《仪器仪表学报》 EI CAS CSCD 北大核心 1997年第5期 514-517,共4页
准静态C—V测量中的工频噪声滤除新方法*李同合陈光遂高捷(西安交通大学微电子工程系西安710049)0引言半导体界面陷阱密度Dit是表征Si-SiO2界面性质的一个重要参数,该参数对半导体器件,特别是对MOS晶体管特... 准静态C—V测量中的工频噪声滤除新方法*李同合陈光遂高捷(西安交通大学微电子工程系西安710049)0引言半导体界面陷阱密度Dit是表征Si-SiO2界面性质的一个重要参数,该参数对半导体器件,特别是对MOS晶体管特性及稳定性有着重要影响。精确地测量... 展开更多
关键词 准静态 C-V测量 半导体 ATF 界面陷阱密度 测量
在线阅读 下载PDF
部分耗尽SOI器件背栅界面陷阱密度的提取 被引量:1
16
作者 赵洪利 高林春 +3 位作者 曾传滨 刘魁勇 罗家俊 韩郑生 《微电子学》 CAS CSCD 北大核心 2015年第6期817-819,828共4页
利用基于复合理论的直流电流电压法,提取SOI器件背栅界面陷阱密度。给出了具体的测试原理,以0.13μm SOI工艺制造的部分耗尽NMOS和PMOS器件为测试对象,分别对两种器件的背界面复合电流进行测试。将实验得到的界面复合电流值与理论公式... 利用基于复合理论的直流电流电压法,提取SOI器件背栅界面陷阱密度。给出了具体的测试原理,以0.13μm SOI工艺制造的部分耗尽NMOS和PMOS器件为测试对象,分别对两种器件的背界面复合电流进行测试。将实验得到的界面复合电流值与理论公式作最小二乘拟合,不仅可以获得背界面陷阱密度,还可以得到界面陷阱密度所在的等效能级。结果表明,采用智能剥离技术制备的SOI器件的背界面陷阱密度量级均为1010cm-2,但NMOS器件的背界面陷阱密度略大于PMOS器件,并给出了界面陷阱密度所在的等效能级。 展开更多
关键词 直流电流电压方法 复合理论 界面陷阱密度 等效能级
钝化介质层对功率GaAs MESFET的栅-漏击穿特性影响 预览
17
作者 费庆宇 黄云 《电子产品可靠性与环境试验》 2004年第2期 1-5,共5页
用直接测定GaAs MESFET的栅-漏极电容-频率(C-f)和高频电容-电压(C-V)的方法,研究了钝化层-半导体界面的慢界面陷阱电荷对栅-漏反向击穿特性的影响,为解决GaAs MESFET的栅-漏反向击穿特性不良和不稳定提供了依据.
关键词 栅-漏极电容-频率 高频电容-电压 栅-漏反向击穿电压 界面陷阱密度 钝化层
在线阅读 下载PDF
DCIV技术表征MOS/SOI界面陷阱能级密度分布 被引量:3
18
作者 赵洪利 曾传滨 +3 位作者 刘魁勇 刘刚 罗家俊 韩郑生 《半导体技术》 CAS CSCD 北大核心 2015年第1期63-67,共5页
基于直流电流电压(DCIV)理论和界面陷阱能级U型对称分布模型,可以获取硅界面陷阱在禁带中的分布,即利用沟道界面陷阱引起的界面复合电流与不同源/漏-体正偏电压(Vpn)的函数关系,求出对应每个Vpn的有效界面陷阱面密度(Neff),通过N... 基于直流电流电压(DCIV)理论和界面陷阱能级U型对称分布模型,可以获取硅界面陷阱在禁带中的分布,即利用沟道界面陷阱引起的界面复合电流与不同源/漏-体正偏电压(Vpn)的函数关系,求出对应每个Vpn的有效界面陷阱面密度(Neff),通过Neff函数与求出的每个Neff值作最小二乘拟合,将拟合参数代入界面陷阱能级密度(DIT)函数式,作出DIT的本征分布图。分别对部分耗尽的n MOS/SOI和p MOS/SOI器件进行测试,得到了预期的界面复合电流曲线,并给出了器件界面陷阱能级密度的U型分布图。结果表明,两种器件在禁带中央附近的陷阱能级密度量级均为10^9cm^-2·e V^-1,而远离禁带中央的陷阱能级密度量级为10^11cm^-2·e V^-1。 展开更多
关键词 直流电流电压(DCIV) 金属氧化物半导体/绝缘体上硅(MOS/SOI) 有效界面陷阱密度 最小二乘拟合 U型分布
上一页 1 下一页 到第
使用帮助 返回顶部 意见反馈